In the manufacture of integrated-circuit devices such as, e.g., semiconductor memory and logic chips, various forms of etching play a significant role in forming microscopic device features such as, e.g., conductor paths. Typically, such features are made by depositing a layer of a desired material on a substrate, further depositing a photosensitive "resist" layer, patterning the resist layer by projection imaging and developing, and transferring the developed pattern to the desired layer by etching. In the case of conductor paths, resulting features may serve, e.g., to supply electrical power, to define channel regions of metal-oxide-semiconductor (MOS) transistors, or to carry signals between points within a chip, or between the chip and its environment.
While, desirably, etched features such as conductor paths have uniform width, actually realized linewidth may vary for a number of reasons as related to lithographic processing as well as to etching. For example, lithographically defined width is influenced by projection lens imperfections (e.g., spherical aberration and focal curvature), by the lens resolution limit, by wafer non-flatness and wafer topography, by focus and exposure selection, by resist processing variations (e.g., with respect to development temperature, and resist contrast and thickness), by feature proximity to adjacent features, and by underlying topography. Also, linewidth as etched is influenced further by etch bias, by etch uniformity (run-to-run, wafer-to-wafer, as well as within a wafer), resist profile, resist processing, and by feature proximity.
With respect to uniformity of feature width, particular attention will be paid in the following to proximity effects which, as mentioned above, play a role in connection with lithography as well as with etching.
Lithographic proximity effects play a significant role especially when feature width and spacing approach the limit capability of photolithographic equipment, and such effects have received increasing attention as design-rule feature-size limit has been and continues to be reduced from one device generation to the next. With respect to the influence of lithographic proximity effects, see, e.g.,
P. D. Robertson et al., "Proximity Effects and Influences of Nonuniform Illumination in Projection Lithography", Proceedings of SPIE, Vol. 334 (1982), pp. 37-43 and
Y. Nissan-Cohen et al., "Variable Proximity Corrections for Submicron Optical Lithographic Masks", Digest of Technical Papers, 1987 Symposium on VLSI Technology, Karuizawa, IEEE, 1987, pp. 13-14.
As to proximity effects affecting etching, such effects may be attributed to the formation of sidewall films during plasma etching, typically by deposition of polymeric materials, or redeposition of nonvolatile etch products; see, e.g.,
R. J. Schutz, "Reactive Plasma Etching", Chapter 5 in: VLSI Technology, 2nd edition, S. M. Sze, ed., McGraw-Hill, New York, 1988.
As discussed, proximity effects may lead to inaccurate delineation of patterns in a resist layer and, ultimately, to inaccurate feature dimensions. Thus, in the interest of faithful reproduction of specified features, it is desirable to minimize variability of etched feature size due to proximity effects, and the invention described below is motivated by such desire.